Reply
Posts: 2
Registered: ‎02-09-2015

Using si5345 what is timing of clock outputs using zero delay mode

[ Edited ]

I have an Si5345 and a Xilinx FPGA.  The FPGA provides IN0 and OUT9 is fedback to use Zero Delay mode.  The other 9 ouptputs are integer multiples of IN0 one of which is fed back to the FPGA to act as a high frequency clock.  I need to know what overall delay there might be from the rising edge of IN0 to each of the OUTs.  Thanks, Dave

Highlighted
Posts: 2
Registered: ‎02-09-2015

Re: Using si53445%2C what is timing of clock outputs using zero delay mode

if there is a moderator, please remove the random %2C in the the title and the number should be si5345.  Sorry for finger trouble! Dave