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Posts: 472
Registered: ‎01-18-2004

Si5351B, synchronous output clocks from the VCXO

I built up a little board to test how the Si5351B would work as an audio word clock sync PLL. In this application, a "word" clock at the sample frequency is applied to a PLL which synthesizes modulator clock at 512 times the sample rate. The converters use the I2S serial interface to transfer data, and a bit clock at 64 times the sample rate is required.

 

I programmed the 5351B to generate 24.576 MHz (on CLK0 and CLK1), 3.072 MHz (on CLK2 and CLK3) and 48 kHz (on CLK4 and CLK5). Without the VCXO, the outputs are as I expect, all edges are aligned. That is, the two 48 kHz outputs are aligned, the 3.072 MHz outputs are aligned, and the 24.576 MHz outputs are aligned. And on the edges of the 48 kHz output I see that the other clocks are aligned to it. In other words, these are synchronous clocks, as described in the data sheet.

 

So the idea is to generate 24.576 MHz from 48 kHz. The lowest frequency acceptable on the 5351C's clock input is 10 MHz, so that won't work. But the 5351B has a VCXO and a control voltage input, so it should be possible to

 

I rigged up a little breadboard based on the 74LV4046A (with a 3.3V supply). The external word clock (at 48 kHz) fed the 4046's SIG input, and one of the 48 kHz outputs from the 5351B feeds the 4046's COMP input. I use the 4046's PC2 output with a simple single-pole loop filter to drive the 5351's Vc input. Using Clock Builder I set up the registers to indicate that the clock source would be the VCXO, not the internal PLL.

 

The good news is that this PLL worked -- it locked right up and generated the clocks at the correct frequencies. The bad news is that the clocks are asynchronous. None of them line up at all.

 

So the questions:

 

a) Is it the case that all clocks generated with the VCXO as the source are always free-running (asynchronous), or can they be made to be synchronous?

 

b) If they can be made to be synchronous, how do I do that?

 

(I suppose that in this application, the Si571 would work, but an external divider is required. No big deal, but the idea of having all of the clocks generated in one device is appealing.)

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,185
Registered: ‎04-27-2004

Re: Si5351B, synchronous output clocks from the VCXO

[ Edited ]

I'm lost here.

You already generate 24.576MHz, but want to recreate (another?) 24.576MHz from 48kHz ?

For that, you use a 24.576MHz crystal+Si5351B+LV4046 ?

 

If you use VCXO mode, did you check that has linear lock, and is not just some average lock?

Also check the phase pulses for variation.

 

With such a narrow Vc /ppm span, I could imagine a case where average Vc is correct, but it has a lot of band-bang modulation ?

 

The exact operation of the VCXO is unclear to me, some diagrams have it going into synth ?

Data says 

"All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input."

All sounds like there could be more 'elasticity' here than you want ?

Maybe a classic analog varicap + crystal might 'lock' better ?  

What ppm catch range do you need ?

 

Posts: 472
Registered: ‎01-18-2004

Re: Si5351B, synchronous output clocks from the VCXO


jmg wrote:

I'm lost here.

You already generate 24.576MHz, but want to recreate (another?) 24.576MHz from 48kHz ?

For that, you use a 24.576Mhz crystal, 


Yes, but -- in professional digital audio applications, it is often necessary to synchronize two (or more) converters (ADC or DAC) to a common sample-rate "word clock." Some device provides a 48 kHz square wave word clock output, and other devices slave to that master.

 

The complication is that audio converters do not run at the sample rate. They are all oversampling types, which means that a modulator clock running at 512 times the sample clock is required.

 

Thus a PLL is used to synthesize that 512x modulator clock, 24.576 MHz, from the incoming word clock. An intermediate clock of 64x the sample rate, in this case 3.072 MHz, is required because it's the serial audio data shift clock. The word clock itself is used as the frame clock, delineating when the sample time actually starts.

 

So in this application, the 5351 acts as a PLL-based frequency synthesizer.


If you use a VCXO, did you check that has linear lock, and is not just some average lock?

Also check the phase pulses for variation.

 

With such a narrow Vc /ppm span, I could imagine a case where average Vc is correct, but it has a lot of band-bang modulation ?


I didn't see any bang-bang once locked, it looked like the control voltage was a steady DC with no glitching.


The exact operation of the VCXO is unclear to me, some diagrams have it going into synth ?

Data says "All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input."

All sounds like there could be more 'elasticity' here than you want ?


I don't think it's elasticity -- I think that in this mode, the dividers aren't synchronized like they are when the clock source is from the 5351's internal PLLA. Which doesn't make sense, why would the outputs be synchronous when the clock source is PLLA but free-running when the clock source is PLLB?


Maybe a classic analog varicap + crystal might 'lock' better ?


Something like the standard 74HC4046 PLL would work, too, but there are several considerations. One is that the jitter of the 4046 VCO is terrible. A common solution is to use a VCXO at the nominal 24.576 MHZ frequency and some kind of divider on its output to feed into the external phase comparator (the other PC input being the input 48 kHz clock). Jitter here is much better than the VCO solution, but there is a problem I have not mentioned:

 

Digital audio systems often run at sample frequencies other than 48 kHz. Obviously the CD standard 44.1 kHz is common, and higher-end systems demand higher sampling frequencies, so 96 kHz and 192 kHz are becoming common. 

 

To support 44.1 kHz (and its multiples) and 48 kHz (and its multiples) in the same system, you need two VCXOs and the logic to switch between them, and dividers whose depth varies with sample rate. 

 

Futhermore, it is often not necessary to synchronize to an external word clock; a converter should be able to run off of an internally-generated modulator clock. This means two more XOs, as most VCXOs need the control input to be driven accurately.

 

All of the clock switching and such gets really messy, and this is why the 5351 is convenient: it generates ALL of the required clocks, no external dividers necessary, and it can output those clocks with low jitter regardless of whether it is synchronizing to an external word clock or not. Simply programming the registers is all that is necessary.

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,185
Registered: ‎04-27-2004

Re: Si5351B, synchronous output clocks from the VCXO

[ Edited ]
I don't think it's elasticity -- I think that in this mode, the dividers aren't synchronized like they are when the clock source is from the 5351's internal PLLA. Which doesn't make sense, why would the outputs be synchronous when the clock source is PLLA but free-running when the clock source is PLLB?

I think maybe the way they do the VCXO, which sounds like a PLL modulation, not a Xtal-shift, is the issue, based on those tests ?

You could still try a Xtal+Varicap approach, as even if the PLL is included, the lack of internal VCXO footwork should simplify things.

I guess first check if Xtal+trimmer with PLL can manually lock, and keep dividers sync'd ?

Posts: 472
Registered: ‎01-18-2004

Re: Si5351B, synchronous output clocks from the VCXO


jmg wrote:
I don't think it's elasticity -- I think that in this mode, the dividers aren't synchronized like they are when the clock source is from the 5351's internal PLLA. Which doesn't make sense, why would the outputs be synchronous when the clock source is PLLA but free-running when the clock source is PLLB?

I think maybe the way they do the VCXO, which sounds like a PLL modulation, not a Xtal-shift, is the issue, based on those tests ?


You are correct, the control voltage does not pull a crystal, it varies a PLL. They use the term "VCXO" because that's the function of the "black box" but it's not really a VCXO. My guess is that the mechanism which implements the spread-spectrum modulation is the same that is used to "control" the "VCXO." This also explains why you have to use PLLA for spread-spectrum outputs and PLLB for VCXO-controlled outputs.

 

I opened a support case, and the engineer's response is that the lack of output sync "may be due to VC varying." In other words, when the loop truly locks, the VC should be pretty much solid DC, and in that case, the outputs should be synchronized. If the VC varies "significantly," and he suggested "over 0.3 V or so in amplitude over time" then the lower frequency output (the 48 kHz) will respond every cycle but the higher frequencies cannot, hence a lack of sync.

 

This implies that my loop bandwidth should be reduced so that it doesn't try to track tiny variations or noise.

 

The whole point of having a VC input and a VCXO feature in this device is to allow users to build a synchronizing PLL out of it, and part of that is the ability to have all of the synthesized clocks output by that PLL to be synchronized.


You could still try a Xtal+Varicap approach, as even if the PLL is included, the lack of internal VCXO footwork should simplify things.


I could, sure, and that means not using this part, which is fine. But what makes this part attractive is that it's all-inclusive: VCXO, dividers, output buffers for multiple frequencies. And it's inexpensive, too.


I guess first check if Xtal+trimmer with PLL can manually lock, and keep dividers sync'd ?


The support engineer suggested tying the VC input to a stable voltage (ground, VDD, whatever) to see if the outputs were synchronized, and if so, that indicts the phase detector/loop filter circuit, with an eye towards reducing loop bandwidth. That's my homework assignment for this weekend, I suppose.

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Posts: 1,185
Registered: ‎04-27-2004

Re: Si5351B, synchronous output clocks from the VCXO


You could still try a Xtal+Varicap approach, as even if the PLL is included, the lack of internal VCXO footwork should simplify things.

I could, sure, and that means not using this part, which is fine. But what makes this part attractive is that it's all-inclusive: VCXO, dividers, output buffers for multiple frequencies. And it's inexpensive, too.


I was meaning adding a varicap to the Si5351 Xtal Osc, you still use Si5351, and for outputs == Xtal, you skip the PLL, but for ones needing a Xtal change, you use the PLL.

 

Simply adding 2 trimmers to Si5351 should give a quick idea of the Xtal pull range possible.

Posts: 472
Registered: ‎01-18-2004

Re: Si5351B, synchronous output clocks from the VCXO


jmg wrote:

I was meaning adding a varicap to the Si5351 Xtal Osc, you still use Si5351, and for outputs == Xtal, you skip the PLL, but for ones needing a Xtal change, you use the PLL.


In this case, why use the Si5351? Again, the reason for using the 5351 is that it's a one-chip (OK, phase detector is separate) solution, including the dividers. Remember I2S needs LRCLK at the sample frequency (which can be 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz), BCLK (64 times the sample frequency) and MCLK (512 or 256 times the sample frequency). And it can be configured to use the VCXO or not.

 

Alternate solutions require the dividers, two XOs (24.576 MHz and 22.5792 MHz) and two VCXOs (the same two frequencies), and logic to mux the clock outputs.


Simply adding 2 trimmers to Si5351 should give a quick idea of the Xtal pull range possible.


the pull range is noted in the datasheet, and it's adjustable!

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,185
Registered: ‎04-27-2004

Re: Si5351B, synchronous output clocks from the VCXO

[ Edited ]

In this case, why use the Si5351? Again, the reason for using the 5351 is that it's a one-chip (OK, phase detector is separate) solution, including the dividers. Remember I2S needs LRCLK at the sample frequency (which can be 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz), BCLK (64 times the sample frequency) and MCLK (512 or 256 times the sample frequency). And it can be configured to use the VCXO or not.


You have just answered your own question - the Si5351 gives the dividers, and an option to use PLL when the Xtal is not the right multiple.


the pull range is noted in the datasheet, and it's adjustable!


Not for the circuit I propose. The datasheet range is for the SiLabs internal PLL based VCXO, which you have reported is not up to the task, hence the need for a different solution.