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10-07-2015 03:55 PM
I am evaluating the SI5324 using the SI5324-EVB. Everything seems to be working well. It is multiplying a recovered clock that I need and it is keeping the jitter well within acceptable limits. However, I am trying to build an turn-key engineering brassboard using the evaluation board and I am running into some trouble.
I need to be able to program the evaluation board with my own frequency plan WITHOUT the USB connection. There is a serial port for that! The problem is that in order to put the CPLD into a high-impedance mode in order to use the serial port on the board, I have to send it a command through the USB port. This high impedance state is not preserved after a power cycle.
I am certain that I can fix this issue either by cutting traces or reprogramming the CPLD. However, I don't know that I could put the board back into its original state after such an alteration. I hate to sacrifice the USB functionality of the evaluation board because the evaluation board it is an incredibly useful tool in my lab.
I am hoping to either get the binary or the source to the CPLD so that my modifications are only temporary.
If I could make a suggestion, two modifications to the board firmware would make this board a lot more useful. One would be the ability to put my own frequency plan into non-volatile memory so that it would power up in a useful state without using the USB port. The other would be a jumper that placed the CPLD into a high-impedance state so the serial programming port could be used by the host system.
10-08-2015 02:02 PM
DSPLLsim has a feature which will write the generated register map into the local EEPROM, once this is done then the EVB will bout up in that mode. The feature is circled in the attached.
Also attached is the Si5324 EVB Users Manual and am wondering if page 9 and modifications on pin 11 (R47 and R37) will help with the 2nd issue.
10-08-2015 02:21 PM
Thanks for the reply.
I did not see the EEPROM feature earlier and it was not called out in the user's manual. It works and I am able to get the board to power up into a useful state.
I also discovered that the CPLD was not locked. I was able to read a binary image of the firmware and save it to a jedc file. I have been able to put my own firmware on the CPLD and later revert back to the default image without issue.
It would still be useful to have source code for the CPLD since I am not (yet) able to completely replicate its functions, but I can do everything that I need to do to get the prototype working.