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Posts: 471
Registered: ‎01-18-2004

AD PLL app note

[ Edited ]

In a post in the 'annoucements' forum, Tabitha asks, 'Have an Application Note idea?'

Not an idea, but perhaps some clarity. Section 3 of the Si514 data sheet is 'All-digital PLL applications,' and it refers to AN575: An Introduction to FPGA-Based ADPLLs.

The app note is pretty good, except for one thing: the source code isn't available. I opened a support request back in May 2012 to get that code, and was told, 'Unfortunately, the Verilog source code for that ADPLL is not ready for release, and we don't have the time or resources at present to finalize and support it.' I followed up by saying that I didn't need support, really, just to see what they were thinking. The final follow-up was that the code wasn't being released at that time.

So is there any way, 18 months later, to kick out that code, even if it's not ready for prime time?

I'm playing with an ADPLL concept based on the Si514 and I'm looking for ideas.

-a

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,175
Registered: ‎04-27-2004

Re: AD PLL app note

The Si514 is a nice part, but seems rather hard to get ?

So a slight morph of Tabitha's, 'Have an Application Note idea?', and on a similar Si50x line, would be to pair the F850 and the Si504.

The F850 even looks like it would clock from the Si504, right up to full Fo(100MHz), with care in the SFRs - just needs a Data sheet extension.

Add a pin for 1pps from a GPS engine, and you could have a locked synthesizer.
Posts: 2,027
Registered: ‎07-14-2007

Re: AD PLL app note

Originally Posted By: jmg
The F850 even looks like it would clock from the Si504, right up to full Fo(100MHz), with care in the SFRs - just needs a Data sheet extension.

I assume the 100MHz are for the SI504? I don't know the SI504, but on the first reading I thought the 100MHz are for the F850, but this can't be smile

Regards,

Scotty
Posts: 544
Registered: ‎10-12-2004

Re: AD PLL app note

Hi Andy,

I've forwarded this request to the Timing applications group, and I'll let you know when I have more information.

~Tabi
Tabitha Parker
Senior Manager of MCU and Micrium Applications
Silicon Laboratories
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,175
Registered: ‎04-27-2004

Re: AD PLL app note

Originally Posted By: Scotty
Originally Posted By: jmg
The F850 even looks like it would clock from the Si504, right up to full Fo(100MHz), with care in the SFRs - just needs a Data sheet extension.

I assume the 100MHz are for the SI504? I don't know the SI504, but on the first reading I thought the 100MHz are for the F850, but this can't be smile


100MHz can be for the F850, if you get only slightly creative.
(see my other thread asking for the spec).
http://forum.silabs.com/ubbthreads.php?ubb=showflat&Number=52980#Post52980

If you look at the F850 (and other micros) they have the Prescaler before the Fsys, and the external clock avoids any Xtal amplifier issues.

On one of their devices, Atmel spec 142Mhz Fi, [Core <= 32MHz] for external Clk and Divider pre-chosen.

SiLabs must have a related number for what the part can take into the divider, (set to /4 or /8) ? I'm guessing similar to Atmel.

The Si504 'boots' at a user-ordered default freq, so you need to define the Division ratio before you send commands to ramp the Fi, but being able to control and verify the Fo using a tiny micro has obvious appeal.
Posts: 471
Registered: ‎01-18-2004

Re: AD PLL app note

Originally Posted By: Scotty
Originally Posted By: jmg
The F850 even looks like it would clock from the Si504, right up to full Fo(100MHz), with care in the SFRs - just needs a Data sheet extension.

I assume the 100MHz are for the SI504? I don't know the SI504, but on the first reading I thought the 100MHz are for the F850, but this can't be smile


My guess is that if you enable the SYSCLK divider and ensure that SYSCLK (after the divider) is < 25 MHz, a higher-frequency EXTCLK is perfectly fine.

-a
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,175
Registered: ‎04-27-2004

Re: AD PLL app note

Originally Posted By: Andy Peters

My guess is that if you enable the SYSCLK divider and ensure that SYSCLK (after the divider) is < 25 MHz, a higher-frequency EXTCLK is perfectly fine.


Exactly - but the data should specify what value is possible.
(just as Atmel do)

In SiLabs case, there are some obvious targets to aim for...

* 100MHz+ to allow Si504 to clock F850
* 160MHz+ to allow Si5351 to clock F850
* 200MHz+, because it is a nice round number..
Posts: 2,027
Registered: ‎07-14-2007

Re: AD PLL app note

Originally Posted By: jmg
100MHz can be for the F850, if you get only slightly creative.
...
If you look at the F850 (and other micros) they have the Prescaler before the Fsys, and the external clock avoids any Xtal amplifier issues.

Ah, now I see the detail. I assumed the F850 clock circuit is the 'standard' implementation from most of the other MCUs.

Regards,

Scotty