Si5341 FAQ

by <a href=""><font color="#000000"><font size="2">Hero Employee</font></font> </a> hari121 ‎06-12-2017 05:48 PM - edited ‎06-12-2017 05:50 PM

The datasheet can be found here


Q: How do I "program" Si5341 ?

A: The Si5341 can be programmed in two ways:

     i. Volatile memory programming {The volatile memory can be programmed any number of times after power up} 

     ii. Non-volatile memory (NVM) programming. The NVM can be reprogrammed "twice". After each NVM program, a power cycle (either an actual power supply re-sequence or assertion of POR) will lead to the contents of NVM being implemented and therefore a pre-defined frequency plan can be enforced on power up. CBPro and the Family Reference Manual provide help to either use a silicon labs tool or to use 


Q: How do I access Quality information (RoHS, etc) for Si5341? 

A:    i. Navigate to this link:

       ii. Log into the website when prompted (if you do not have an account, please register and navigate to the link again and please login when prompted). 

       ii. Search for the "full part number" that you have ordered from the Si5340 family in the     link: 

       iii. The search results will include any quality and reliability information that you choose. 


Q: How do I find FIT, MBTF data for Si5341? 

You can find it in the link below:

You will need to login when prompted to access the above information. 


Q: What if I did all of the above and still unable to get the information I need ? 

A: e-mail with your question (and copy you sales, distribution partners). 



Q: Can I obtain the CBPro code so that I can get a reference on how to program the Si5341 ? 

No. However, CBPro has a Command Line Interface (CLI) that can help you implement changes to Si5341 without using the GUI and the CLI can be used to invoke changes to Si5341 and you can harness the power of CBPro in your S/W. 

If you feel the need for flexibility and are ready to trade-off with optimal jitter performance (as an example), then a strategy for implementing the planner is attached as a pdf. 



Q: How much of an increased jitter should I expect with lack of optimization in frequency synthesis? 

A: The fractional synthesis will generally lead to about 20-30% increased jitter. 


Q: How do you define crosstalk and how detrimental is crosstalk for a frequency plan ? 


  1. CBPro will look at any two adjacent frequencies: F0 and F1, CBPro will look for “F1 ~ F2”, “(3*F2 ~ 2*F1)/2” , “(2*F2 ~ F1)/2” , where a~b means the difference between a and b
  2. This is because, the phase spurs (which are non-linearities caused due to “mixing” of the two output frequencies) will have harmonics of the “fourier series of F1, F2”
  3. While in sinusoids, the fundamental frequency difference F1~F2 is the only cause for the spur, for clock signals, we do need to account for harmonics (due to the sharp edges).
  4. whenever, harmonic mixing (as from step 1) could causes a spur that is in the band of 12KHz -  20MHz, the CBPro SW will flag a warning i.e. the differences from step 1 are within 12KHz – 20MHz, for example, if F1 = 100 MHz and F2 = 101MHz, F1~F2  = 1 MHz and it is within the 12KHz – 20MHz band 

In Si5341, the noise floor is very low. Therefore, spurious tones can increase jitter by up to 2-3X (i.e. up to 200-300 fs compared to a sub-100 fs).


CMOS drivers make the crosstalk problem worse. Hence, avoiding CMOS drivers is critical if there is a need for high performance clocking solutions.