The VDD0A or VDD0B should be set to GND if an output bank is unused, an entire bank can be unpowered to save current.
An unused clock input pair should be left open. The Si53315 has an anti-chatter input specifically designed for this application; if there is no input the outputs will not chatter due to noise injected on the unused clock input.
Unused clock outputs can be left open if there is no PC trace length. If there is an output trace then standard termination can be used to reduce reflections and noise, e.g. a 100 ohm resistor is placed at the “receiver” end of an LVDS output. Note: Differential outputs should be terminated in a like manner, e.g. if one output is used the other should not float and should be terminated in a like manner.
The input can be a pulse input, data, spread spectrum or a non-periodic clock input. There is no AC coupling nor ZDM PLL inside the Si53315, the output switches upon clock input switching (meeting the data sheet VCM and threshold criteria).
The CMOS outputs are in-phase between outputs and between banks.
The OE has an internal 25 Kohm pull-up resistor and can be unterminated for active outputs. An additional pull-up resistor, such as 1K, can also be used. However, for troubleshooting purposes it may be desirable to enable and disable the outputs using the OE feature - in this case OE would terminated to GND through a resistor such as 1 Kohm.
The SFOUT pins have internal 25 kohm pull-up and pull-down resistors, setting an internal bias to VDD/2. For midstate level the SFOUT pins would be left open. A smaller resistor, such as 1K or lower, should be used when terminating SFOUT to VDD or GND – a 10 Kohm pull-up or pull-down may not achieve the appropriate logic levels.