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Posts: 7
Registered: ‎06-18-2017

si4455 GPIO divided clock output

I designed a PCB using the si4455. In WDS there is an option for tuning the crystal frequency by adjusting the internal capacitors. WDS has the following description:

 

"The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance and to adjust the frequency of the crystal oscillator. The total internal capacitance is 11 pF and is adjustable in 127 steps (70fF/step). The crystal frequency adjustment can be used to compensate for crystal production tolerances.
There are two suggested way to perform frequency calibration:
a) measure the divided clock output on the GPIO with a frequency counter and tune the crystal load capacitance as long as the accurate clock frequency achieved."

 

There is another option which is irrelevant for me. I'd like to tune it using the divided clock output on a GPIO port, but there is no option that I can see for this.

 

Is there something I'm missing? maybe I need to transmit the data and use TX_DATA_CLK as the data rate also uses the crystal timing for a reference?

 

The following are the options I have for GPIO output:

 

 

DONOTHING0Behavior of this pin is not modified.revB1A
TRISTATE1Input and output drivers disabled.revB1A
DRIVE02Pin is configured as a CMOS output and driven low.revB1A
DRIVE13Pin is configured as a CMOS output and driven high.revB1A
INPUT4Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate.revB1A
SDO11Outputs the Serial Data Out (SDO) signal for the SPI bus.revB1A
POR12This output goes low during Power-On Reset and goes high upon completion of POR.revB1A
EN_PA15This output goes high when the internal PA is enabled.revB1A
TX_DATA_CLK16Outputs the TX Data Clock signal. This signal is a square wave at the selected TX data rate, and is intended for use in TX Direct Synchronous Mode (i.e., in conjunction with a pin configured for TX Data Input).revB1A
RX_DATA_CLK17Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU.revB1A
EN_LNA18This output goes low when the internal LNA is enabled.revB1A
TX_DATA19Outputs the TX data bits pulled from the TX FIFO and sent to the TX modulator. This is an output signal (primarily for diagnostic purposes) and is NOT used as an input for TX Direct Sync/Async mode.revB1A
RX_DATA20Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock.revB1A
RX_RAW_DATA21Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock.revB1A
VALID_PREAMBLE24This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs.revB1A
INVALID_PREAMBLE25Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled.revB1A
SYNC_WORD_DETECT26This output goes high when a Sync Word is detected, and returns low after the packet is received.revB1A
CCA27Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal.revB1A
IN_SLEEP28This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state.revB1A
PKT_TRACE29Outputs packet trace data when not in sleep state. Output low when in sleep state. 
TX_STATE32This output is set high while in TX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch).revB1A
RX_STATE33This output is set high while in RX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch).revB1A
RX_FIFO_FULL34This output is high while the number of bytes stored in the RX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise.revB1A
TX_FIFO_EMPTY35This output is high while the number of bytes of empty space in the TX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise.revB1A
CCA_LATCH37This output goes high if the Current RSSI signal exceeds the threshold and remains high (i.e., is latched) even if the Current RSSI signal subsequently drops
below the threshold value. The signal returns low upon detection of the Sync Word or upon exiting RX state.