Posts: 9
Registered: ‎10-22-2016

Si1060 minimum RAM retention voltage in sleep mode

The data sheet (Si106x-8x.pdf) advertises the ability of the devices with DC-DC converters to retain RAM state with VBAT as low as 0.3V.  The puzzle: the Si1060 has neither a DC-DC converter nor a VBAT pin, just VDD_MCU.  What's the rest of the story for Si1060 if it enters low-power sleep mode (SmaRTClock, radio and all peripherals except PMU0 powered off) before VDD_MCU falls below V_rst?