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Posts: 9
Registered: ‎10-22-2016
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Si1060 minimum RAM retention voltage in sleep mode

The data sheet (Si106x-8x.pdf) advertises the ability of the devices with DC-DC converters to retain RAM state with VBAT as low as 0.3V.  The puzzle: the Si1060 has neither a DC-DC converter nor a VBAT pin, just VDD_MCU.  What's the rest of the story for Si1060 if it enters low-power sleep mode (SmaRTClock, radio and all peripherals except PMU0 powered off) before VDD_MCU falls below V_rst?

 

Thanks,

Rich

Posts: 214
Registered: ‎11-04-2014

Re: Si1060 minimum RAM retention voltage in sleep mode

Hello Rich,

Fair question - it can get a little confusing when a single document is used to describe (define) a group of devices with differing feature sets.  Section 13.5 "Sleep Mode" of the datasheet states:

"RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT (or VDD_MCU on Si1060/61/80/81 devices) does not fall below VPOR."

Let me know if you're still unclear about any Si1060 details.

Best regards,
- Phillip