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04-19-2017 07:54 PM
I can't get the SI4432 to power down to any mode lower than READY. This is my command to sleep:
B0,00 //Register 30, no receive or transmit
87,00 //Register 07, All off
I've tried setting enphpwdn=1, enlfc=1, checking interrupts, setting and restting txon and rxon in register 07, even tried it 100 times.
There are two symptoms which correlate: The current into the SI4432 is about 0.9A when the sleep sequence above is executed, and if I query Reg 62 to read the pwst bits it always reads 001, which indicates RDY. That makes sense with the current measurement, but why? It should be reading LP (000).
If I leave enlfc=0 and mclk at the default value of 011 then I can see the GPIO clock output drop from 1MHz in receive mode to 0 (constant low) when the above sleep sequence is executed. In addition, my scope says that the 30MHz osc is nice and clean in receive or transmit, then shuts off when the above sleep sequence is executed.
According to Section 2.1 of the data sheet (Operating Modes), Fig 9 shows that the 1uA and lower states, (Sensor, Sleep, Standby) are accessible when the main 30MHz osc turns off. My scope says the osc turns off when 0x00 is written to register 07 (setting xton=0), but the status bits and the current consumption disagree.
The register configuration is attached, and yes I'm executing a POR procedure by clearing the pending ipor and ichiprdy interrupts, running a swres rest, then clearing interrupts again.
I'm hoping that someone here can spot something I've done wrong in the setup, or perhaps shed some light on this.
04-26-2017 02:39 AM
First read the status registers to clear them then write 00 to 0x87.
As you write the crystal oscillator stops. This suggests that the chip itself is in sleep or sensor mode. It is possible that an external component causes the extra current. Do you have anything connected to the GPIOs or are there pull-up or pull-down resistors that may draw extra current?