What is causing spectral splatter?
Let’s have a look at this concept through a simple example. Suppose you transmit a pure CW signal. Your spectrum will look like a single tone at the carrier frequency. When you start switching this CW tone on and off with a square wave pattern the spectrum of the square wave pattern will be convolved with the CW spectrum resulting in a sinx/x like overall spectrum profile around the carrier. If the switching is not part of the core modulation (in this example a CW tone) than the increased spectral components induced by switching are not desired and referred to as spectral splatter.
If you substitute the CW tone in above example with an arbitrary modulated signal and the switching pattern with an RF packet start / stop ramp you arrive at real example that will behave the same way as the simplified case.
How do we control spectral splatter?
Spectral splatter can be kept at bay by controlling the ramp profiles in time domain at the beginning and end of the packets. As a rule of thumb the longer the ramp the narrower its splatter spectrum. The goal here is to keep the splatter spectrum within the modulated signal’s own spectrum so no out of band splatter occurs at all. Although this cannot be achieved for all modulating formats on Si446x there are turning knobs the issue can be mitigated with.
What are the knobs on mitigating spectral splatter on Si446x?
1) The first knob is field PA_TC in API property PA_TC. This field directly controls the ramp time on the PA. WDS configures this filed to a value of 0x1D by default which leaves two notches until the maximum ramp time is achieved at 0x1F. If a loner ramp is needed adjust this field manually to one of the higher values.
Note1: If you have increased this value you may want to readjust API property PA_RAMP_DOWN_DELAY to prevent the PA from shutting off before the ramp down has finished. Increase this value if you see issues at ramp down.
Note2: This scheme applies to all ramp up/down events in OOK modulation.
2) On Si446x revC2A (and Si4467/68 revA2A) a digital power ramping feature was introduced that sequentially steps through PA_POWER_LVL values (from min to max with a configurable step size) with a configurable dwell time on each of these steps. Much longer ramp times can be achieved with this approach.
You can enable this feature by setting field DIG_PWR_SEQ in API property PA_MODE. You can configure the dwell time and the step size in API property PA_DIG_PWR_SEQ_CONFIG.
Note that with this method the built-in PA ramp (discussed at (1)) is not applied between the steps only at the 1st step at minimum power level.
The digital power ramp feature has a bug that is not fixed with released FW patches: the power ramp only takes effect at ramp up but does not take effect at ramp down.
There is a SW workaround to the issue:
1) Do the following SPI write 0xF1474B00. Wait for CTS.
2) Make a transition to SLEEP state
3) Make a transition back to READY state