Reply
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Super Star</font></font> </a> DW8
Posts: 15
Registered: ‎04-15-2016

Stange!!! Right input lags left input by one sampling CLK in CP2114+CS42L55 evaluatin kit

I found a very strange issue with the CP2114 (B01) + CS42L55 setup. When I inject the same signal to both input channels, there is always some phase difference between the two channels of data acquired.  In the screenshot below, an external 10kHz sine wave was fed to both input channels of CS42L55, as you can see from the oscilloscope screen, the data in the right channel lags those in the left channel by one sampling CLK. I have tested the Silicon Labs' evaluation kit and a few prototypes we made based on CP2114 (B01) + CS42L55, the results were the same.

 

RightLagsOneCLKAsCompareToLeft.png

 

What make it more strange is, if you loopback HP Out to Analog IN on the evaluation kit using a stereo cable, and generate a 10kHz signal from HP Out and acquire it through AIN (I used some well-known sound card oscilloscope and signal generator software), no phase difference is found.  The two curves match each other very well. A further study showed that there is also a phase difference between the two channel's output from HP Out. The left output lags the right output channel by a sampling CLK. This explains why there is no phase difference between the two in the stereo loopback test.

 

CONFIG 0 is used in the above tests. My question is, "Is the phase difference between the two input channels caused by (1) configuration, (2) CP2114, or (3) CS42L55? " How to resolve the issue? 

 

Thanks!

 

 

 

Posts: 201
Registered: ‎07-27-2016

Re: Stange!!! Right input lags left input by one sampling CLK in CP2114+CS42L55 evaluatin kit

Hi @DW8,

 

I was hoping that you could help me understand the nature of your issue better. You said that the signal is off by one clock cycle - can you please let me know which clock cycle you are referring to? There is MCLK, LRCLK and SCLK. There are two audio interface modes - I2S and Left-justified mode. In case of I2S mode, the MSB of SDOUT and SDIN are delayed by one clock (SCK) cycle after the LRCLK transitions as compared to the Left-justified format. 

 

Screen Shot 2017-08-21 at 7.24.28 PM.png

Was this what you were referring to?

 

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Super Star</font></font> </a> DW8
Posts: 15
Registered: ‎04-15-2016

Re: Stange!!! Right input lags left input by one sampling CLK in CP2114+CS42L55 evaluatin kit

Thanks Marao.  I was actually referring to the sampling clock 48kHz (16 bit).  Normally, the stereo data would be arranged as:

 

... Left16bits(N-1), Right16bits(N-1), Left16bits(N), Right16bits(N), Left16bits(N+1), Right16bits(N+1)...

 

but my measurements showed that they were actually arranged as:

 

... Left16bits(N-1), Right16bits(N-2), Left16bits(N), Right16bits(N-1), Left16bits(N+1), Right16bits(N)...

 

Any idea?

 

 

Posts: 471
Registered: ‎01-18-2004

Re: Stange!!! Right input lags left input by one sampling CLK in CP2114+CS42L55 evaluatin kit

Look at the two waveforms @marao posted. LRCLK is high for the left-justified format and low for standard I2S. If you inadvertently set the audio serial port to use left-justified instead of I2S, but your software only knows about I2S, then it gets the samples in the wrong place (right instead of left and the converse), and that looks like a one-sample delay on one channel.

 

So make sure both the CP2114 and CS42L55 are configured to both use either I2S _or_ left-justified, they must match.

Highlighted
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Super Star</font></font> </a> DW8
Posts: 15
Registered: ‎04-15-2016

Re: Stange!!! Right input lags left input by one sampling CLK in CP2114+CS42L55 evaluatin kit

@Andy_Peters, thanks for the reply.

 

I am using CP2114+CS42L55 evaluation board from Silabs. CONFIG 0 is used, therefore both CP2114 and CS42L55 should be in I2S format. The CP2114 on this evaluation board is B01.  If I inject a mono 10kHz sinewave into both analog input channels of the board (i.e. AIN socket), I will get a one-sample offset on time axis between the two input channels.   I attach here another screenshot obtained from a free software called Audacity here. It clearly shows that the two input channels are misaligned by one sample in time.

 

CP2114PhaseDifference.png 

Could that be a bug in B01? I noticed that the B02's datasheet has corrected an error in Left-Justified format in B01's datasheet (see the comparison below). I am not sure whether this document correction meant a bug correction in B01 or not.

 

CP2114DatasheetComparison.png

I have not tested this with a CP2114 B02 + CS42L55 board yet. Hopefully it is just a bug in B01 and B02 has resolved this issue. Anybody can confirm this?