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Posts: 6
Registered: ‎10-05-2017

CPT112S Pull I2C SCL low after rising edge on SCL

My current board design have a number of slave that is connected on the same I2C bus as the CPT112S. one of which is the temperature sensor. We occasionally received a bad data from the temperature sensor and we later found of that there is a glitch on the I2C clock. It is as though one of the slave randomly detecting a rising edge and driving it low. I soldered a series resistors on each of the slaves to identify the one that driving the clock low right after a rising edge, and we found CPT112S is the slave causing the glitch. Generally it would be ok if the slave hold the clock low to make adjustment to the clock rate, however, it seems that the CPT112S is holding just after the rising edge that cause other slave to read it as a clock. Please see the attachment for more detail on how the series resistor affect the waveform. The clock rate is running at 88kbit so it is far within the 400kbit. Please let us know if there is anything that we may have done to cause the CPT112S pulling the clock late or is this a bug in the CPT112S firmware. We can reproduce this issue on both revision A1 and A2. Thank you, Tan
Posts: 238
Registered: ‎07-27-2016

Re: CPT112S Pull I2C SCL low after rising edge on SCL

hi @Tan1,

 

This is strange and we haven't come across such an issue in the past. How often do you see this happening? do you have multiple boards across which you are seeing similar behavior? Just to confirm, you have 1.5k pull ups on the I2C pins of the CPT112S, right?

 

Best,

 

Manasa

Posts: 6
Registered: ‎10-05-2017

Re: CPT112S Pull I2C SCL low after rising edge on SCL

The 1.5k pull resistor is populated, and that how we determined that the CPT112S is pulling the clock low. By adding 2k resistor, the voltage divider is at 1.9V when the CPT112S is pulling the clock low. This issue is rare, and we can only consistently reproduce this by continuingly talking with other device. On average we see it 1 out of 1000 transaction.
Posts: 488
Registered: ‎02-21-2014

Re: CPT112S Pull I2C SCL low after rising edge on SCL

Super weird.

 

Do you have a capture of this happening where you can tell what the data byte being sent from the master is? What is the value of the preceding byte?

 

Are you using repeated starts?

 

One theory is that a repeated start is seen by the 112s as a new start, and the data byte corresponds to its address or something weird like that.

Posts: 6
Registered: ‎10-05-2017

Re: CPT112S Pull I2C SCL low after rising edge on SCL

The CPT112S pulling clock low can either be in the address or data when communicating to other devices or continuing scan data from CPT. See attachment for image when a 2k2 series resistor is soldered to the CPT SCL. I have checked if there is either a start or stop bit before this occurrence, but it doesn't seem to be any.
Posts: 488
Registered: ‎02-21-2014

Re: CPT112S Pull I2C SCL low after rising edge on SCL

What is the ADDR of the CPT112S device? The default? Something else?

Posts: 488
Registered: ‎02-21-2014

Re: CPT112S Pull I2C SCL low after rising edge on SCL

Oh, I see, on your ticket it is mentioned that the CPT device's ADDR is 0x70. Very strange, since the clock in your image is being pulled low during bit 7 of the address 0x90 being sent...

Posts: 488
Registered: ‎02-21-2014

Re: CPT112S Pull I2C SCL low after rising edge on SCL

Could you zoom in on this screen capture to show the SDA and SCL lines in more detail?

Posts: 6
Registered: ‎10-05-2017

Re: CPT112S Pull I2C SCL low after rising edge on SCL

See attachment for couple of captures with various glitch width. Please note series resistor was removed from the CPT SCL line.
Posts: 488
Registered: ‎02-21-2014

Re: CPT112S Pull I2C SCL low after rising edge on SCL

Sorry - I didn't see any timescales in the captures: does the 112S low period change when you change the I2C clock speed?

 

Are you using haptics (buzzer)?

Posts: 6
Registered: ‎10-05-2017

Re: CPT112S Pull I2C SCL low after rising edge on SCL

Hi Brian, Please see the attachment for one of the zoom in capture. As mentioned in the early document, the clock speed on this capture is 80khz, so it is significantly lower than 400khz as specified in CPT112 datasheet. We also try to increase the speed to 160khz, and it has the same result that it hold low for half a cycle (3us).
Posts: 6
Registered: ‎10-05-2017

Re: CPT112S Pull I2C SCL low after rising edge on SCL

We use the MCU to drive the buzzer, so we don't enable the CPT to drive the buzzer.