CP240x configuration and pin interfacing for low power applications

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> MitchC on ‎12-30-2016 09:20 AM

Question

When using the CP240x LCD controller for a battery powered application where lowest power operation is the goal, what is the best device configuration and pin interfacing options to use?  Specifically:

 

1) Is it sufficient to use either 20 kHz or 40kHz self-oscillate mode (i.e. without a crystal or external clock) for clocking the LCD controller and I2C communications functions?

2) During I2C communications, is it necessary to switch to the 20MHz (divided by n) Internal oscillator?
3) Does this potential clock switch happen in automatic way or does it need the use of the “/PWR” input?
4) If the “/PWR” pin should not be used, is it preferred connecting it to GND or VDD?
5) Shall the unused “/CLK” pin be connected preferentially to GND or VDD?
6) Can the unused “XTAL1” (input) be connected to GND or VDD?
7) Can the unused “XTAL2” (output) be connected to GND or VDD or has to be left floating?
8) Is it advised connecting the unused “/INT” pin to GND or is it better leave it floating?
9) Shall the metal pad (thermal pad) at the bottom of the component be connected to GND (externally) or has to be left floating?

Answer

When using the CP240x devices in low power applications, please note that there is a known issue where sometimes when re-entering sleep mode (after a wake-up) the part does not fully go into shutdown. The partial sleep state is generally in the 1.3 uA range, though it can vary. This issue never occurs when entering sleep for the first time after a reset.

There is an errata being put in place for this issue.

We have a partial work around which is to reset the MCU before entering sleep mode. This will ensure that sleep mode is entered properly, but it does incur some extra power consumption since the device consumes higher than average current for a brief time when coming out of reset. If the part is going to be asleep for only a brief period then the reset may waste more power then it saves.

An additional workaround for systems in development would be to power the CP240x from an extrnal MCU and completely remove the supply to the device instead of putting it in sleep mode. Please note that if this is the case, the CP240x will need to be reconfigured after each power on, and LCD control will be unavailable in the OFF mode.

 

1) Is it sufficient to use either 20 kHz or 40kHz self-oscillate mode (i.e. without a crystal or external clock) for clocking the LCD controller and I2C communications functions?


The 20 kHz or 40 kHz self-oscillate mode of the SmaRTClock is sufficient for standard LCD controller functionality. This functionality is available in Normal mode (see sec 9.1, p.50 of the CP240x datasheet) as well as Ultra Low Power (ULP) LCD mode (see section 9.3, p. 51). Transitions into and out of this ULP LCD and other ULP/Shutdown modes are handled using different combinations of control register settings and rising/falling edges on the /PWR pin (please consider the errata condition mentioned above when deciding on how to utilize low power modes vs, device power off). I2C communications are available between the host MCU and the CP240x only in Normal mode, when the internal 20 MHz oscillator (which is separate from the SmaRTClock oscillator) is active.

2) During I2C communications, is it necessary to switch to the 20MHz (divided by n) Internal oscillator?

I2C communications are available between the host MCU and the CP2403 only in Normal mode, when the internal 20 MHz oscillator (which is separate from the SmaRTClock oscillator) is active. Data can be transferred by the SMBus/I2C at up to 1/20 of the system clock, or the maximum speed allowed by the SMBus specification, whichever is slower.

3) Does this potential clock switch happen in automatic way or does it need the use of the “/PWR” input?

If you are going to use ULP LCD mode, the device will continue to use the SmaRTClock (RTC) timebase to enable LCD control. After wakeup from any of the ULP modes, firmware must reconfigure any registers that do not retain their state in ULP modes, including the CLKSEL register (clock select) and IOSCCN register (internal oscillator control). Follow the instructions on page 50-53 for procedures to enter and exit ULP modes using the /PWR pin (as well as consider the errata condition mentioned above).

4) If the “/PWR” pin should not be used, is it preferred connecting it to GND or VDD?

Entry into ULP modes is triggered by a rising edge transition on the /PWR pin. If unused, this pin can be driven to GND or VDD.

 

5) Shall the unused “/CLK” pin be connected preferentially to GND or VDD?

The lowest power option for the /CLK pin is to tie it to VDD.

6) Can the unused “XTAL1” (input) be connected to GND or VDD?

You can leave the unused XTAL1 pin floating.

7) Can the unused “XTAL2” (output) be connected to GND or VDD or has to be left floating?

You can leave the unused XTAL2 pin floating.

8) Is it advised connecting the unused “/INT” pin to GND or is it better leave it floating?

You can leave the unused /INT pin floating.

9) Shall the metal pad (thermal pad) at the bottom of the component be connected to GND (externally) or has to be left floating?

Connect the metal pad on the back of the device to GND.