CP2120 SPI command/response is corrupted when toggling CS between SPI write and SPI read

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> ChrisM on ‎12-12-2016 03:01 PM

Question

When issuing a command to the CP2120, the read data is corrupted.  What can cause this issue?

Answer

The CP2120 relies on chip select being asserted during the entire command write and response read process.  Toggling chip select between this write and read will corrupt the internal state machine and return invalid data.

 

Make sure that chip select is asserted for the entire duration of each SPI command (including SPI write and SPI read transfer).

 

The CP2120 has logic to switch the MISO output pin between push pull and open drain mode. The device only drives the MISO pin in push pull mode when it's expected to return data to the SPI master. If the SPI master toggles CS more than once during a SPI command write and then read, the device state machine will enter an invalid state and send bytes with the pin configured as open-drain, which is not a strong enough driver to meet the minimum rise time for high SPI clock rates, resulting in corrupted data being sent to the SPI master.