What are the main differences between I2C and SMBus?

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> jonorem on ‎10-21-2014 01:53 PM

Question

What are the main differences between I2C and SMBus?

Answer

  While Silicon Lab's MCU's support both I2C and SMBus operation is useful to understand the differences between the two protocols. 

 

I2C Specification

SMBus Specification

 

The primary differences between SMBus and I2C have to do with various timing requirements. The most important are listed here:

 

  SMBus defines a minimum bus clock frequency FSMB of 10 KHz. I2C does not specify any minimum bus

frequency. Besides maintaining effective bus throughput, this SMBus specification parameter can be used
as a simple way to detect a bus idle condition (in addition or in lieu of detecting each STOP condition) as
well as to implement bit timeout.

 

  SMBus defines a data hold time, the time during which SMBDAT must remain valid from the falling edge
of SMBCLK, of 300 nS. I2C defines this hold time as zero.

 

  Maximum clock frequency for SMBus is defined at 100 KHz. I2C provides two modes of operation. The
STANDARD MODE up to 100 KHz and the FAST-MODE up to 400 KHz.


  SMBus defines a clock low time-out, TTIMEOUT of 35 ms. I2C does not specify any timeout limit.

 

  SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device. I2C does not
have a similar specification.

 

  SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device. Again I2C
does not have a similar specification.

Comments
by Rene_Koch
on ‎06-08-2017 09:48 PM

"SMBus defines a data hold time, the time during which SMBDAT must remain valid from the falling edge
of SMBCLK, of 300 nS. I2C defines this hold time as zero."

 

According to the latest I2C specification from NXP (http://www.nxp.com/documents/user_manual/UM10204.pdf), the Standard-Mode I2C requires a minimum of 5 us for data hold time. If I want to implement this using the SMBus feature from EFM8BB1, I need to lower my SYSCLK to less than 2.4 MHz with enabling EXTHOLD. In my case my problem is even worse, as the specifications of a sensor that I would like to use requires 50 us (unbelievable). Is there any alternative other than using another sensor, or implementing the I2C protocol completely in firmware?