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Posts: 3
Registered: ‎10-06-2017

c8051f206 chip expandable to 64k code space?

Hello all, I came across some interesting information on the C8051F206 chip that allows settings to be changed in the silicon labs IDE in order to "open" the memory of the chip to 64k rather than the extremely small amount it is specified in the chip. From the IDE go to Project -> Tool Chain Integration -> Compiler -> Customize -> Memory Model -> Code size limits. Here I can change this from small: Program 2k or less to 64k. I am curious on a few things: 1) Are there limitations or byproducts of changing this setting and running in real time? 2) Why does the spec sheet for this device make no mention of the extra space? Where can I find more information on this?
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,185
Registered: ‎04-27-2004

Re: c8051f206 chip expandable to 64k code space?


Re: c8051f206 chip expandable to 64k code space?
.... From the IDE go to Project -> Tool Chain Integration -> Compiler -> Customize -> Memory Model -> Code size limits. Here I can change this from small: Program 2k or less to 64k. 

That is just the Compiler setting,  not the physical device setting.

2k options is historic in 8051 tools, allows use of AJMP, and some evaluation versions used limited size.

Silabs have had 64k tools for some time now.


 2) Why does the spec sheet for this device make no mention of the extra space? 

Because there is no 'extra space' Robot Happy    c8051f206 has 8k Flash.

You have confused a compiler setting, with a physical flash size.

 

Of course, it would be wonderful to be able to increase the physical flash in any 8051, from a PC GUI, but the real world does not work that way Robot wink

 

Posts: 3
Registered: ‎10-06-2017

Re: c8051f206 chip expandable to 64k code space?

My understanding is that the compiler creates an "artificial" memory boundary, which this setting changes. What I don't understand is why the 8051 line is 64k architecture but the f206 spec sheet has no mention of this? In fact it states it is limited to 1280 bytes. Why is this the case?
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<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,185
Registered: ‎04-27-2004

Re: c8051f206 chip expandable to 64k code space?


My understanding is that the compiler creates an "artificial" memory boundary, which this setting changes. What I don't understand is why the 8051 line is 64k architecture but the f206 spec sheet has no mention of this? In fact it states it is limited to 1280 bytes. Why is this the case?

The 8051 architecture can support up to 64k of CODE(flash) and 64k of XDATA(RAM), but it is rare to find a controller with both those maxed out.

XDATA is especially costly to add, and the largest XDATA in mainstream 8051 MCUs is ~ 8k

 

It is up to the chip supplier to choose how much Flash and RAM they include, as they do add cost, and that can remove customers....

eg 

The F206 has 8k CODE and  1024+256 bytes of RAM, which means 1024 bytes of XDATA.