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Posts: 6
Registered: ‎05-23-2015
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Need sample code for SMBus1 for C8051F390

Hi All,

 

I tried to modify sample C8051F390/SMBus0 code (SiLabs\MCU\Examples\C8051F39x_37x\SMBus\F39x_SMBus_Master_Multibyte.c) to work with SMBus1 through P2.2, P2.3 pins, but with no luck: it does not produce interrupt on STA1.

 

What is important: similar SMBus0 code works OK in the same hardware configuration with the same physical pins (P2.2, P2.3): produces interrupt on STA, communicates with external I2C chips, ...

 

And yes, I've taken into account SFR paging, interrupts enable, timers and other documented differences between SMBus0 and SMBus1. But maybe I've overlooked one of the differences ... So, I would greatly appreciate sample code for SMBus1 Master for C8051F390.

 

 

Thank you

 

Alex S

Posts: 301
Registered: ‎09-04-2013

Re: Need sample code for SMBus1 for C8051F390

[ Edited ]

Could you please provide your SMBus1 code, including SMBus1 initialization and ISR?

 

 

Posts: 6
Registered: ‎05-23-2015

Re: Need sample code for SMBus1 for C8051F390

Looks like I found the source of the problem. It appears that it is necessary to properly set SFRPAGE to be able to access STA1, STO1 and all other SMBUS1 bits with 8051 bit commands.

 

 

Posts: 7,804
Registered: ‎08-13-2003

Re: Need sample code for SMBus1 for C8051F390

It appears that it is necessary to properly set SFRPAGE to be able to access

 

It always surprises me that this comes as a surprise, every darn SFR in devices with SFRPAGE has references to SFRPAGE all over the place.  s it that today's 'programmers' (note the quotes) expect that there is no need to read ANY documentation, just open the window and the fried pigeon will fly in.

erik
Posts: 6
Registered: ‎05-23-2015

Re: Need sample code for SMBus1 for C8051F390

Hi ErikM,

 

Could you please point out the paragraph in C8051F390 data sheet which requires to assign SFRPAGE before accessing SBIT (not the SFR!)?

 

Here is what paragraph 19.1 says:

 

The procedure for reading and writing an SFR is as follows:

1. Select the appropriate SFR page number using the SFRPAGE register.

2. Use direct accessing mode to read or write the special function register (MOV instruction).

 

STA1 and STO1 are *NOT* SFRs, they are BITs!

 

Alex

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,033
Registered: ‎04-27-2004

Re: Need sample code for SMBus1 for C8051F390


Could you please point out the paragraph in C8051F390 data sheet which requires to assign SFRPAGE before accessing SBIT (not the SFR!)?
...

STA1 and STO1 are *NOT* SFRs, they are BITs!

 


The S prefix in that SBIT, stands for SFR BIT, and that  gives you one huge clue.

The other clue is the general 8051 Architecture feature whereby all bits are contained within a Byte.

Posts: 6
Registered: ‎05-23-2015

Re: Need sample code for SMBus1 for C8051F390

In fact I was misguided by irrational hope that SiLabs found some way to avoid SFRPAGE overhead  for simple conditional jump instructions like JB and other single-bit operations.

The reason for such hope: they did not mention single-bit operations in 19.1

And they definitely could avoid such overhead if overall amount of bit-addressable flags fit 8-bit addressing limit imposed by 8051 architecture.

And yes, I learned the hard way that this is not the case ...

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Posts: 1,033
Registered: ‎04-27-2004

Re: Need sample code for SMBus1 for C8051F390


...

And they definitely could avoid such overhead if overall amount of bit-addressable flags fit 8-bit addressing limit imposed by 8051 architecture.


Nope - there is no free lunch ( and no spare Space)

The 8051 architecture allows 128 bits of SFR, and those are all already mapped, so SFRPAGE is the only way to give boolean access to more than 128 SFR-bits.