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Posts: 5
Registered: ‎06-03-2017

C8051F362-GM/C8051F362-GMR RESET Sources

I am the electrical engineer at Orbital ATK and we are using the MCU C8051F362-GMR and having issues at cold temperatures (-32 C).

It seems like the MCU is Resetting itself. I am wondering If anyone can provide more detail about the default values for all registers associated with RESET, one important register is: VDDMONCN (VDD monitor Control).

It seems like we may have a temporary voltage drop on VDD and at cold the Vst Threshold must be higher, then if VDD drops below this it may RESET the MCU. How long does the VDD need to drop below Vrst for a RESET?

 

As I mentioned, I would also like to know the default setup for the rest of the 7 possible RESET sources (located on page 128 of the datasheet). Please get back to me as soon as possible!

 

Posts: 8,172
Registered: ‎08-13-2003

Re: C8051F362-GM/C8051F362-GMR RESET Sources

[ Edited ]

It seems like we may have a temporary voltage drop on VDD and at cold the Vst Threshold must be higher, then if VDD drops below this it may RESET the MCU. How long does the VDD need to drop below Vrst for a RESET?

probably less than a microsecond

 

As I mentioned, I would also like to know the default setup for the rest of the 7 possible RESET sources (located on page 128 of the datasheet). 

it is in the datasheet "reset value"

 

Please get back to me as soon as possible!

makes no difference

erik
Posts: 5
Registered: ‎06-03-2017

Re: C8051F362-GM/C8051F362-GMR RESET Sources

The "Reset Value" says Variable so I need to know what it is when it comes up before it is ever written to/set. See Page 131 of Datasheet. Also I need to know where you got your answer for how long the VDD needs to be below Vrst to put the MCU in RESET. I need to know if it is actually less than 1 microsecond, thank you.
Posts: 8,172
Registered: ‎08-13-2003

Re: C8051F362-GM/C8051F362-GMR RESET Sources

[ Edited ]

page 129 The VDD Monitor is enabled following a power-on reset.

 

the reset value is 'variable' because VDDSTAT depend on the unknown state of VddMON

 

re 1uS I wrote 'probably' since there should be NO, NONE, NADA dips below Vdd(min)

erik
Posts: 5
Registered: ‎06-03-2017

Re: C8051F362-GM/C8051F362-GMR RESET Sources

Thanks, but we still don't know the default initial value of the VDD MON register (I need to know before it has a Power On Reset event.) Also I know that in a perfect environment the VDD should not dip but I am using this in a unique environment where VDD could possibly dip for a small amount of microseconds so I need to know how this VDD MON circuit works and how quickly it will initiate a RESET signal.
Posts: 3,147
Registered: ‎02-07-2002

Re: C8051F362-GM/C8051F362-GMR RESET Sources

Both reset SFR's are variable since their values depend on the reset source. There is more info in the text around them. In some conditions some bits are even undefined and can have any value. E.g. when POR is set the other bits are undefined and should be ignored.

Posts: 8,172
Registered: ‎08-13-2003

Re: C8051F362-GM/C8051F362-GMR RESET Sources

I am using this in a unique environment where VDD could possibly dip for a small amount of microseconds

 

then code in such a way that a 'spurious' reset will not hurt functionality

erik
Posts: 5
Registered: ‎06-03-2017

Re: C8051F362-GM/C8051F362-GMR RESET Sources

Thanks for your answers. We are in the middle of a build and have 13% failures at cold due to the MCU resetting. I am thinking the reset failures are due to some having some VDD Monitors enabled and a low enough vdd drop. A software solution is too late for this build but understanding the issue is key to the next. We can add code to turn the VDD monitor off and this could fix the issue, we just need to make sure this is the root cause of the failures, this is why it is necessary to know what the initial value of VDD Monitor is (before reset or writing to it) and also how long VDD needs to be below Vrst to initiate a RESET
Posts: 8,172
Registered: ‎08-13-2003

Re: C8051F362-GM/C8051F362-GMR RESET Sources

We can add code to turn the VDD monitor off and this could fix the issue

 

then you would have "code runaways" instead

 

is your power supply 5V, 3V3 or something higher regulated down?

erik
Posts: 3,147
Registered: ‎02-07-2002

Re: C8051F362-GM/C8051F362-GMR RESET Sources


hous wrote:
this is why it is necessary to know what the initial value of VDD Monitor is (before reset or writing to it)

This really is in the surrounding text in the datasheet 12.2:

 

The VDD Monitor is ..abled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD Monitor is ..abled and a software reset is performed, the VDD Monitor will still be ..abled after the reset.

 

I'll leave it to you to find out what should be on the dots.

 

Btw. How well are your decoupling caps doing at -25C?

Posts: 5
Registered: ‎06-03-2017

Re: C8051F362-GM/C8051F362-GMR RESET Sources

Thanks for chiming in you have provided no help at all and provided an incorrect reference, VDD MON is section 12.1 page 131 of the datasheet, thanks though.
Highlighted
Posts: 3,147
Registered: ‎02-07-2002

Re: C8051F362-GM/C8051F362-GMR RESET Sources

In Rev 1.1 of the datasheet for the C8051F360 which I used, section 12.2 starts at page 130. On page 131 there is SFR definition 12.1.

 

But if you choose to be angry with me because I tried to help you with what you could have found out yourself, I will try to remember to ignore you next time you come asking for help. I do this in my spare time you know.

Posts: 8,172
Registered: ‎08-13-2003

Re: C8051F362-GM/C8051F362-GMR RESET Sources

But if you choose to be angry with me because I tried to help you with what you could have found out yourself, I will try to remember to ignore you next time you come asking for help.

 

I'm done too

erik