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Posts: 11
Registered: ‎08-28-2017
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C8051 External Timer Input

I'm using C8051f04x series control in my project and i'm having one strange behavior.

I'm using timer 1 in mode 2 initially and at certain point i change the mode to 1 ( 16 bit), ( disabling the interrupt then turning off the timer and then changing the mode). then i donot generate interrupt but i poll for the TF1 flag.  clock for this timer is from external. This works correctly.. But at random occasion, suddenly TF1 flag is set while i know that it is not supposed to be ( as there was no clock)

I know, this sounds crazy, but i'm facing this issue..I'm wondering is there any erata around this- or what are the other ways that TF1 is gets sets ?

Posts: 8,134
Registered: ‎08-13-2003

Re: C8051 External Timer Input

clock for this timer is from external. ..... But at random occasion, suddenly TF1 flag is set while i know\

noise

erik
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,175
Registered: ‎04-27-2004

Re: C8051 External Timer Input


... ( disabling the interrupt then turning off the timer and then changing the mode).


Do you also clear TF1, before you start sampling to ensure no carry-over effects ?

 

Posts: 11
Registered: ‎08-28-2017

Re: C8051 External Timer Input

Yes - I do clearing the flag

Posts: 11
Registered: ‎08-28-2017

Re: C8051 External Timer Input

This is the piece of code and where i'm seeing the problem - any thing that i'm doing wrong here

 

ANL IE,#075H                  ; (2) disable timer interrupts

JNB FLAG,ABORT

CLR RS1                          ; (1) select register bank 1

SETB RS0

ANL TCON,#00FH ; 

MOV TMOD,#056H         ; 

MOV TH1,#High(65535-28125) ; (2) initial count for approx. 1/2 sec

SETB TR1                       ; (1) start timer 1

 

.....                                   ; <20-25 simple instruction - no loops, no changes on any registers>

Jnb TF1,Ptd1a                ;(2) no  fault detected - jump

Jmp Fault_Detected       ;(2) go handle encoder fault

<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,175
Registered: ‎04-27-2004

Re: C8051 External Timer Input


.. But at random occasion, suddenly TF1 flag is set while i know that it is not supposed to be ( as there was no clock)...

This is the piece of code and where i'm seeing the problem - any thing that i'm doing wrong here

 

ANL IE,#075H                  ; (2) disable timer interrupts

JNB FLAG,ABORT

CLR RS1                          ; (1) select register bank 1

SETB RS0

ANL TCON,#00FH ; 

MOV TMOD,#056H         ; 

MOV TH1,#High(65535-28125) ; (2) initial count for approx. 1/2 sec

SETB TR1                       ; (1) start timer 1

 

.....                                   ; <20-25 simple instruction - no loops, no changes on any registers>

Jnb TF1,Ptd1a                ;(2) no  fault detected - jump

Jmp Fault_Detected       ;(2) go handle encoder fault


How random ?

Very low but non zero failure rates can be due to aperture effects, and above you look to clear and stop in one line.

Remember this is hardware and software interacting, and there can be clock pipeline effects.

I'd be inclined to try an explicit stop-then-clear, as separate and spaced code lines, and I'd also not change modes across the clear.

 

MOV TH1,#High(65535-28125) ; (2) initial count for approx. 1/2 sec

CLR  TF1    ; remove any possible pipeline TF1's

SETB TR1                       ; (1) start timer 1

 

Posts: 11
Registered: ‎08-28-2017

Re: C8051 External Timer Input

Jmg   - Thank you for the response .  This is providing some logic explanation to our problem.

That may be weakness in Silicon controller. 

 

To provide back ground, recently i ported the code from DS80C310 to C8051F04x due to obsolescence 

The code in DS80C310 - was running correctly for 15+ year!!.  

 

 

 

Posts: 8,134
Registered: ‎08-13-2003

Re: C8051 External Timer Input

[ Edited ]

That may be weakness in Silicon controller. 

The code in DS80C310 - was running correctly for 15+ year!!.  

 

again noise the SiLabs controller will pick up a much narrower noise pulse than the Dallas chip

 

erik
Posts: 11
Registered: ‎08-28-2017

Re: C8051 External Timer Input

i agree Noise would play role, but here it happens within ~20us after i stop and start the timer which is roughly calculate down to that noise should be in terms of Ghz - and i guess controller can detect pulse only which has 2 clock cycle width?  - so it is very unlikely

Posts: 8,134
Registered: ‎08-13-2003

Re: C8051 External Timer Input

if your 'desired' pulse is wide enough, for proof try a RC filter

erik
<a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero</font></font> </a> jmg
Posts: 1,175
Registered: ‎04-27-2004

Re: C8051 External Timer Input

[ Edited ]

sudhee wrote:

i agree Noise would play role, but here it happens within ~20us after i stop and start the timer ..


That's new information you 'forgot' to mention before... HOW something fails, always gives clues...

 

How consistent is that ~20us, and how often is it that, instead of what you expect ?

What is that ~20us expressed in SysCLKs ?  (or Ext Clks?)

What do you expect - is it ~28125 pulses on the external pin ? 0.5s suggests ~56kHz ?

 

Also, did you try this ?

 

CLR  TR1 
MOV  TMOD,#056H ;
MOV  TH1,#High(65535-28125) ;   initial count for approx. 1/2 sec
CLR  TF1        ; remove any possible pipeline TF1's
SETB TR1       ;  re-start timer 1

Posts: 11
Registered: ‎08-28-2017

Re: C8051 External Timer Input

Hi Jmg,

My apologies not mentioning the 20us :-( 

 

How consistent is that ~20us, and how often is it that, instead of what you expect ?
     - When failure happens, it is very consistent ~20us - i expect 0.5s
What is that ~20us expressed in SysCLKs ? (or Ext Clks?) 
What do you expect - is it ~28125 pulses on the external pin ? 0.5s suggests ~56kHz ? -
    - i expect 0.5s and it corresponds to 56k

 

We tried your first solution which gave positive result. I took the same with silicon lab technical team, they confirmed that, there would be situation when this instruction in execution, if timer overflows - then hardware would take the priority over the software operation. Hence TF1 remains set.

 

Still testing your initial solution, will be continuing to  do for couple more days before calling success.
But below solution looks more optimized, i will try with this as well.

Thank you , appreciate your responses


Really i'm amazed by your analysis!!