What Does "Under Bias" Mean for the 5V Tolerant GPIO?

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Master Employee</font></font> </a> delu on ‎04-13-2017 04:37 PM - edited on ‎04-26-2017 10:13 AM by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> Tabitha

Question

I see in the data sheet of some 8-bit MCUs (e.g. EFM8LB1) that some pins are 5V tolerant under bias. What does this mean?

Answer

In this context, "under bias" refers to the voltage tolerance of the "5V tolerant" device pins in relation to the voltage of VIO (the "bias" in this case).  Thus, as specified in Table 4.19. Absolute Maximum Ratings of the EFM8LB1 datasheet on page 30, the 5 V tolerant pins are tolerant to a voltage of 5.8 V or VIO+2.5 V, whichever is lower.

 

Note: VDD must also be powered in this case, since Table 4.19 in the datasheet lists that the VIO voltage should not exceed VDD+0.3 V.