Using the Port I/O PINRSTMD feature of the EFM8LB1 and EFM8BB3 devices

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> MitchC on ‎10-02-2017 02:02 PM

The EFM8BB3 and EFM8LB1 devices contain a feature to enable the retention of port I/O output state through non-power on resets (POR).  Setting the PINRSTMD bit in the PCON1 register will cause the port I/O state to persist through all resets except for power-on resets.  The following sequence correctly describes the operation of the PINRSTMD feature:

 

1)      Normal operation – MCU running

2)      Firmware sets PINRSTMD bit.  Writes to PxMDIN, PxMDOUT, Pn, and XBARE registers still affect pin mode and output state.

3)      Non POR-reset occurs.  At this point, the PxMDIN, PxMDOUT, Pn, and XBARE registers are reset, but output state of the port pins remains unchanged. PINRSTMD bit remains set.

4)      While PINRSTMD is still set, firmware can write to PxMDIN, PxMDOUT, Pn, and XBARE registers, but no changes will occur to the pin modes or output states.

5)      Firmware clears the PINRSTMD bit.  Pin mode and output state are updated to reflect any changes in PxMDIN, PxMDOUT, Pn, and XBARE registers since the non-POR reset.

6)      Firmware sets PINRSTMD bit.  Writes to PxMDIN, PxMDOUT, Pn, and XBARE registers still affect pin mode and output state. (same as step 2)