How to use EFM8LB1 I2C slave, it looks quite different from SMBus peripheral.
The EFM8LB1 contains a I2C slave peripheral, it includes many interesting features which helps on high speed transfer but may cause confusion to the user who was familiar with legacy SMBus operation. Here we make a brief intro of I2C slave, and attach an I2C slave bootloader example code for reference.
The I2C peripheral contains 2 bytes FIFO and 1 byte shift register for TX/RX individually. The I2C slave support auto ACK/NACK an I2C master, it is controlled by BUSY bit field of I2C0CN0 register. In default, the BUSY is "1" which the device will not respond to an I2C master. All I2C data sent to the device will be NACKed. We should set this BUSY bit as "0", the device will acknowledge an I2C master. For a case, the master keep sending data to device, the device ACK the master automatically for max 3 ACKs since two bytes in FIFO and 1 byte in shift register. And then the SCL is hold low to indicate device is not capable to receive more data. We should check RXE bit field of I2C0FCN1 register to know if there is data in FIFO, read received data from I2C0DIN register.
The auto ACK feature makes difficulty on flow control, as we mentioned above, the SCL is hold low when the RX FIFO is full, so that device can handle the data. What about the master changes read/write direction? There is another feature can helps on this situation. The FACS bit field of I2C0ADM register. The defaults value is "1" which means FORCE_STRETCH. When this bit is set, clock stretching always occurs after an ACK of the address byte until firmware clears I2C0INT bit. With this clock stretching feature, we are able to hand the flow control during read/write direction changes.
There is an I2C slave bootloader example code which base on AN945, please take a look into it and have a reference on how the I2C slave works under polling mode.