C8051F9xx 10-bit ADC performance in one-cell mode

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> marao on ‎12-12-2016 02:37 PM


I am seeing a reduction in SAR10 ADC performance when the device is operating in one-cell mode. What can I do to prevent this degradation?


Any system that puts large switching activity in close proximity to sensitive analog circuitry has the potential for interference issues, and systems using the C8051F9xx devices are no exception. The switching currents of the dc-dc converter can cause interference with external signals that are used as inputs to the SAR10 ADC. Conversions performed on internal signals (such as the integrated temperature sensor) are usually not affected. In addition to following good engineering practices such as careful board layout of the sensitive signals and the use of an appropriate anti-aliasing filter, there are other steps that can reduce or eliminate the interference.


  1. We recommend the use of the external ground reference option available on the P0.1/AGND pin.
  2. You can use the SYNC bit in the DC0CN register to synchronize the ADC sampling to the dc-dc converter when running the dc-dc converter from its local oscillator.


Applying averaging to the signal using the SAR10’s burst mode accumulator feature is effective at eliminating any residual noise using this method. Finally, you can manually synchronize the dc-dc converter and SAR10 clocks by ensuring that both clocks are derived from SYSCLK and the SAR10 clock frequency is an integer multiple of the dc-dc clock frequency. In this method, adjustment of the phase relationship between the start-of-conversion signal and the dc-dc clock can prevent the interference.