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Esteemed Contributor
Tsuneo
Posts: 6,303
Registered: ‎02-15-2004

Re: C8051F120 + CP2200

Another drawback of CP220x is that it's I/O timing is too slow for full-speed of 'F12x-13x. When SYSCLK is set to 100 MHz, the I/O timing which EMIF can generates doesn't fulfill the CP220x requirement.

Read pulse width: 160 ns is require, and 160 ns max - no margin
Write hold time : 40 ns is required, but 30 ns is max

75 MHz SYSCLK is the maximum to satisfy Write hold time.

Code:

Table 26. Non-Multiplexed Intel Mode AC Parameters (CP2200.pdf rev0.41 p97)
TRD RD Low Pulse Width (Read): 160 ns (min)
TDH Data Hold Time (Write) : 40 ns (min)

Table 17.1. AC Parameters for External Memory Interface (C8051F12x-13x.pdf rev1.4 p233)
TACW Address/Control Pulse Width: 16 x TSYSCLK (max)
TWDH Write Data Hold Time : 3 x TSYSCLK (max)


Tsuneo

[This message has been edited by Tsuneo (edited June 29, 2007).]
Frequent Contributor
KevinH
Posts: 87
Registered: ‎07-21-2005

Re: C8051F120 + CP2200

Tsuneo,

The write data hold time you referenced is for multiplexed mode. The non-multiplexed mode timing is 20ns.

It had better work at 98MHZ - all of the examples that Silabs ship for the 'F120 are running at this speed! But you make a good point - the non-multiplexed chip would be required to be able to run at the 'F120's maximum speed.

[This message has been edited by KevinH (edited June 29, 2007).]