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Posts: 2
Registered: ‎08-22-2014
Accepted Solution

spidrv "dummy" baudrate causing assert in USART_BaudrateSyncSet

I'm trying to use spidrv (v4.2.1) with a SPIDRV_SLAVE_USART1 configuration and 48MHz reference frequency and am finding that the "dummy" baudrate in SPIDRV_Init  is causing a subsequent assert failure.

 

if ( initData->type == spidrvSlave )
  {
    usartInit.master = false;
    usartInit.baudrate = 1000;      // Dummy value needed by USART_InitSync()
  }

 

The assert failure occurs in USART_BaudrateSyncSet():

 

  /* Verify that resulting clock divider is within limits */
  EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK));

 

Changing the dummy baudrate in SPIDRV_Init to, say, 1E5, prevents this assert failure. I haven't yet done any further testing with this, but thought I'd pass this along in case anyone else is encountering this problem (or, if needing this change implies I'm doing something I shouldn't be, I'd like to know).

Posts: 1,735
Registered: ‎10-14-2014

Re: spidrv "dummy" baudrate causing assert in USART_BaudrateSyncSet

Thanks for pointing out this,
The USART clock in master mode is derived by dividing the HPERCLK. The clock divider used in the EFM32 USART is a 15-bit integral part and a 2-bit fractional part. For so low speed I think it was out of the range the divider could cover is HPERCLK is also high (48MHz).
Maybe below KB helps.
http://community.silabs.com/t5/32-bit-MCU-Knowledge-Base/USART-clock-speed-in-EFM32/ta-p/165700
WeiguoLu