VMON Functionality on EFM32 Series 1 and EFR32 Wireless Gecko

by <a href="http://community.silabs.com/t5/Welcome-and-Announcements/Community-Ranking-System-and-Recognition-Program/m-p/140490#U140490"><font color="#000000"><font size="2">Hero Employee</font></font> </a> MitchC on ‎03-31-2017 05:07 PM

Question

What do the various VMONxxxx bits in the EMU_STATUS register indicate when they are high or low, and how does the EFM32/EDFR32 voltage monitor (VMON) function?  How can I tell if the VMON threshold event for a given channel was triggered due to a rising or falling event on that channel?

Answer

This discussion will attempt to clarify the functionality of the EMU Voltage monitor VMON channels.  Although this discussion focuses on the IOVDD0 channel, much of this pertains to the other VMON channels as well, though there are some differences.

In the EMU_STATUS register, the VMONFVDD, VMONPAVDD, VMONIO0, VMONDVDD, VMONALTAVDD, and VMONAVDD bits indicate the enable status (1=enabled, 0=disabled) of the VDDFLASH, PAVDD, IOVDD0, DVDD, Alternate AVDD, and AVDD channels of the VMON module, respectively.  The VMONRDY bit (bit 0) indicates if any of the enabled channels above are not yet ready (VMONRDY = 0) or if all enabled channels are ready (VMONRDY = 1).  Thus, if VMONIO0 is 1 (EMU_STATUS[4] = 1), then the IOVDD0 channel is enabled as an input to the voltage monitor.  Please note that these bits are status bits only, and that the VMON channels are enabled and can be configured (i.e. threshold values set) through separate registers.  For instance, the IOVDD0 VMON channel is enabled and you can set the voltage threshold for IOVDD0 using the EMU_VMONIO0CTRL register.  Most channels have a single threshold except for AVDD, for which you can set a programmable hysteresis using two thresholds.  These status bits can not be used to determine if a VMON transition was a rising or falling edge event.

To determine if a VMON voltage threshold crossing was a rising or falling event, you must use the EMU_IF register and the corresponding "VMON...RISE" and "VMON...FALL" interrupt flag bits.  Note that these bits must be cleared by software using the corresponding bits in the EMU_IFC register.  Interrupts can be enabled that correspond to these events in the EMU_IEN register (plus enabling EMU interrupts in the NVIC).  Returning to our discussion of the IOVDD0 channel, for example, VMONIO0RISE in EMU_IF will be set when the IOVDD0 voltage crosses from below to above the programmed IOVDD0 VMON threshold (rising edge detected).  Similarly, the VMONIO0FALL in EMU_IF will be set when the IOVDD0 voltage crosses from above to below the programmed IOVDD0 VMON threshold (falling edge detected).