ESD protection on EFM32LG GPIO pins

by <a href=""><font color="#000000"><font size="2">Hero Employee</font></font> </a> MitchC on ‎12-30-2016 09:24 AM


Figure 32.1 on page 757 of the EFM32LG Reference Manual states "There is no ESD diode to Vdd because if using LCD voltage boost the pin voltage will be higher than Vdd. Nevertheless there is an ESD protection block against over voltage."  


What is this ESD protection block, and is it present on EFM32LG devices without an LCD controller?


The ESD structure that connects the I/O pad to IOVDD is indeed not a simple diode, but is rather a PMOS structure. This is present on the pad whether the device has an LCD controller (and thus the LCD voltage boost feature) or not.

On devices with the LCD voltage boost, an over voltage-tolerant circuit biases the PMOS transistor in the ESD structure to raise the threshold voltage of the ESD diode when the pin voltage exceeds VDD. In general, however, voltage on the I/O pins should be limited to the datasheet maximum values of VDD+0.3, and the maximum VDD voltage of 3.8V should be observed. If the I/O pin voltage exceeds VDD+0.3V, conduction will occur between the pin pad and the VDD rail due to the ESD structure. Please note that this condition is for ESD protection and extended exposure of the pin to voltage in excess of VDD+0.3V can cause permanent damage to the device.